1. Field of the Invention
The present invention relates to clock multipliers, and more particularly to clock multipliers using a filter bias of a phase-locked loop to reduce the size of a delay cell, and methods of multiplying a clock.
2. Description of the Related Art
The present invention relates generally to clock multipliers, and more specifically to clock multipliers that may be useful in a design of a low-power voltage circuit.
A clock multiplier multiplies a frequency of an input clock to generate an output clock having a frequency higher than that of an input clock, and then provides the output clock of the clock multiplier to one or more inner circuits of a semiconductor device.
One example embodiment of a clock multiplier using digital complementary metal-oxide semiconductor (CMOS) standard cells is proposed by Michel Combes et, al. in the paper, “A portable clock multiplier generator using digital CMOS standard cells,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 7, July 1996.
From an aspect of very large-scale integration (VLSI) designs, as operating frequencies in semiconductor devices have been increasing, it has become an important issue to design a clock generator that is insensitive to changes in environmental conditions.